1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device allowing electrical writing and erasing, and in particular to a non-volatile semiconductor memory device performing verifying operation of checking the state of memory cells connected to bit lines, source lines and word lines
2. Description of the Background Art
Flash memories which are non-volatile semiconductor memory devices allowing electrical writing and erasing are non-volatile memories that have recently been researched and developed vigorously because extension of the market can be expected owing to their low cost and electrical erasability.
A conventional flash memory will be described below with reference to the drawings. FIG. 7 shows a sectional structure of a DINOR-type flash memory in the prior art.
Referring to FIG. 7, the flash memory includes an N-type well 101, a P-type semiconductor substrate 102, a P-type well 103, N.sup.+ -type impurity regions 104-115, a thin insulating layer 116, floating gates 117, control gates 118, a polycrystalline silicon layer 119, select gates 120 and a main bit line 121.
N-type well 101 isolates P-type semiconductor substrate 102 and P-type well 103 from each other. N.sup.+ -type impurity regions 114-115 are formed in P-type well 103 with a predetermined space between each other. Floating gates 117 are formed on regions between the impurity regions with extremely thin insulating layer 116 (about 100 .ANG.) therebetween. Control gate 118 is formed above each floating gate 117 with an insulating film therebetween. Owing to the above structure, the memory cells are formed of MOS transistors of a two-layer gate structure. Impurity regions 114-115 are used as drains or sources. Each drain is connected to the third layer, i.e., polycrystalline silicon layer 119 serving as a sub-bit line. Polycrystalline silicon layer 119 is connected to main bit line 121 via select gate 120. Each sub-bit line is generally connected to 8 to 64 memory cells, which form one sector (block).
Writing and erasing operations of the flash memory will be described below. FIG. 8 shows writing/erasing operations of the conventional DINOR-type flash memory. FIG. 9 shows a threshold voltage of the conventional DINOR-type flash memory during programming and erasing.
Referring to FIG. 8, information is stored in the flash memory by injecting electrons into a floating gate 123 or removing electrons therefrom, More specifically, when floating gate 123 contains electrons injected thereinto, the threshold voltage of memory transistor viewed from a control gate 122 is high. In other words, a current does not flow if it is higher than the gate voltage Vread as shown in FIG. 9. This state is called an erased state, in which data corresponds to "1". When electrons are removed from floating gate 123, the threshold voltage viewed from control gate 122 decreases. More specifically, the current flows if it is lower than the gate voltage Vread as shown in FIG. 9. This state is called a programmed state, in which data corresponds to "0". In the flash memory, the above two states are detected, and written information is read by a sense amplifier.
Referring to FIG. 8, general writing and reading operations of the DINOR-type flash memory will be described below more specifically. In the erasing operation, a high voltage of about 10 V is applied as a control gate voltage Vg to control gate 122, and a negative P-well voltage Vb and a negative source voltage Vs each being about -8 V are applied to the P-well and source, respectively. As a result of application of these voltages, a channel is generated in the memory cell, and a high voltage of about 18 V is applied across control gate 122 and channel, so that electrons are injected into floating gate 123 by the tunnel effect.
In the writing operation, a negative control voltage Vg of about -8 V is applied to control gate 122, and a positive drain voltage Vd of about 6 V is applied to the drain. As a result of application of these voltages, a high voltage of about 14 V is applied across the drain and control gate 122, so that electrons are removed from the floating gate by the tunnel effect. In this operation, P-well voltage Vb of the P-well is the ground voltage, and source voltage Vs of the source is in the floating state. By the application of the predetermined voltages described above, writing and erasing can be effected on the memory cell.
In the conventional DINOR-type flash memory, as described above, when electrons are removed by the tunnel effect, the electrons may be removed excessively and thus the floating gate may be charged positively. This is called "over-write". Since the threshold voltage viewed from the control gate is negative, a leak current flows through a memory cell which was over-programmed during the writing/reading, so that correct operation cannot be performed. Therefore, write verify is performed with the sense amplifier to check whether the correct writing operation was performed during writing or not, and erase verify is performed with the sense amplifier to check whether the correct erasing operation was performed during erasing or not. In general, one sense amplifier is provided for a plurality of memory cells, i.e., a plurality of bit lines, and write/erase verifying operations are repeated multiple times for effecting write/erase verify on the memory cells to be checked.
Since the write verifying operation with the sense amplifier described above requires a long time, the conventional NAND-type flash memory uses a write verify circuit described below.
The write verify circuit for performing the aforementioned write verifying operation will be described below. An example of the conventional write verify circuit in the NAND-type flash memory is disclosed in "A Quick Intelligent Program Architecture for 3 V-only NAND-EEPROMs, 1992 Symposium on VLSI Circuits Digest of Technical Papers, pp. 20-21". FIG. 10 shows a structure of a write verify circuit of the above conventional NAND-type flash memory.
Referring to FIG. 10, the conventional write verify circuit includes transistors Q61-Q68 and Q71-Q78. Transistors Q81 and Q82 and memory cells MC51-MC5n form a cell array CAA for writing, and transistors Q83 and Q84 and memory cells MC61 and MC6n form a memory cell array CAB at a dummy cell side.
Transistors Q71-Q74, Q79 and Q80 form a flip-flop circuit for latching write data, and transistors Q75 and Q76 form an equalizer circuit for equalizing the flip-flop circuit. Transistors Q62-Q64 and transistors Q65-Q67 form verify circuits for verifying a program, respectively. Each of memory cells MC 51-5n and MC61-MC6n is of an NAND type.
An operation of the write verify circuit thus constructed will be described below. In the erasing operation, all the word lines are set to 0 V, a high voltage is applied to the well of memory cell, and electrons are removed from the whole channel surface into the well by the tunnel effect. In this operation, the threshold voltage of memory cell is negative. Meanwhile, in the writing operation, write data sent from a column decoder 131 is loaded to the flip-flop circuit. In this operation, if the intended threshold voltage is high, "L" is supplied into IOA and "H" is supplied into IOB. Conversely, if the threshold voltage of low value is to be held, "H" is supplied into IOA and "L" is supplied into IOB. Then, a voltage Vrm is raised to a high value of about 10 V, a control signal .phi.a is set to a high voltage, and a control signal .phi.b is set to 0 V. Selected one among the control gates at the cell array CAA side is raised to a high voltage of about 18 V, and all the remaining, i.e., unselected control gates are set to 10 V. In this operation, if the output of flip-flop circuit is a high voltage of about 10 V, a potential difference between the control gate and the channel goes to 8 V, so that injection of electrons into the control gate by the tunnel effect does not occur. Meanwhile, if the output of flip-flop circuit is 0 V, electrons are injected into the floating gate. In this case, all the control gates of cell array CAB are set to 0 V, so that injection of electrons does not occur at all. Here, if the threshold voltage of memory cell is excessively higher than a power supply voltage V.sub.cc (3 V) during reading, the memory cell is not turned on at all, so that reading cannot be done. The reason for this is that the control gate of unselected cell is set to 3 V and the control gate of selected cell is set to 0 V for sensing whether a current flows through the bit line or not. Accordingly, a write verifying operation which will be described below is performed for checking whether or not the threshold voltage of memory cell is raised to an appropriate value not lower than 0 V but lower than 3 V.
FIG. 11 is a timing chart showing the operation of write verify circuit shown in FIG. 10. After the writing, voltages Va and Vb are set to 3.cndot.V.sub.cc /5 (about 1.8 V) and V.sub.cc /2 (about 1.5 V), respectively. At time t1, control signals .phi.pa and .phi.pb are set to "H", and bit lines BLai and BLbi of cell arrays CAA and CAB are charged. At time t2, the selected control gate at the cell array CAA side is supplied with 0.6 V, and the unselected control gate at the same side is supplied with 3 V. All the control gates at the cell array CAB side are supplied with 0 V. If the threshold voltage of memory cell is lower than 0.6 V (i.e., if the writing is not yet sufficient), the charged electric charges are discharged through the memory cell, and the potential of bit lines BLai lowers. Meanwhile, if it is higher than 0.6 V, the charged charges are not discharged through the memory cell, and the potential of bit line BLai is held. At time t3, a control signal .phi.av is set to "H", and transistor Q63 is turned on. If a node NA of the flip-flop circuit is "H" (i.e., if the intended threshold voltage of the memory cell is not high), the bit line is charged again and is maintained at a high potential. Meanwhile, if node NA of the flip-flop circuit is "L" (i.e., if the intended threshold voltage of the cell is high), the bit line BLai is not charged again. At time t4, control signals .phi.p and .phi.n are set to "H" and "L", respectively, and then a control signal .phi.e is set to "H", so that potentials of nodes NA and NB of the flip-flop circuit are equalized to V.sub.cc /2 (about 1.5 V). Then, control signals .phi.a and .phi.b are set to "H", transistors Q64 and Q67 are turned on, and potentials of bit lines BLai and BLbi are compared with each other. In such cases that writing is done, and that the threshold voltage is increased above 0.6 V by the writing, bit line BLai is set to a value (3.cndot.V.sub.cc /5) higher than V.sub.cc /2, and bit line BLai is latched at "H". Meanwhile, if the writing is not yet sufficient, the potential of bit line BLai is lower than V.sub.cc /2, and bit line BLai is latched at "L". In this case, the writing is not yet sufficient, the writing is repeated. The above operation is effected simultaneously on multiple bits, whereby the write verifying operation is conducted.
In the conventional write verify circuit described above, since the check whether the potential of bit line is lowered or not is effect simultaneously on the multiple bits during the write verify, a remarkable problem is caused by a large noise between the bit lines. Thus, when one of the adjacent bit lines lowers from "H" to "L", this may affect the bit line to be held at "H" to lower to "L" in some cases. This influence increases as a space between the bit lines decreases in accordance with increase of the degree of integration, resulting in a problem that integration is suppressed. Since the write verifying operation requires many kinds of voltages and control signals, the circuitry is complicated, so that the circuitry scale increases, which impedes high integration.